• SAE J1850 class B data communications network interface compatible for low speed (<= 125 Kbps) serial data communications in automotive applications.
• Byte-by-byte software message interface.

• Supports wrapper logic for message buffering.
• Supports direct interface with internal soft-core processor or external processor.
• 10.4 Kbps Variable Pulse Width (VPW) bit format (any bit rate can be parameterized).
• 41.6 Kbps Pulse Width Modulated (PWM) bit format (any bit rate can be parameterized)
• Digital noise filter.
• Supports 4X mode (VPW only) for receive and transmit.
• Supports block mode for receive and transmit.
• Hardware Cyclical Redundancy Check (CRC) generation and checking.
• Parameterized symbol timing.
• Supports In-Frame-Response (IFR) types 0, 1, 2 and 3
• Seven interrupt flag one-shots for timing errors, CRC error, lost arbitration, transmit data register empty, receive data register full, IFR received, EOF received.
• Cores consume approximately 195-200 slices in modern Xilinx FPGAs at the minimum required core clock rate.
• Cores are coded in verilog, without part specific instantiations, therefore can be synthesized for virtually any manufacturer FPGA or CPLD.

Notes:

• Drivven will provide a copy of its licensing terms upon request
• Project licenses allow the netlist or source to be used for a single project.
• Site licenses allow the netlist or source to be used for unlimited number of projects.
• Upon request, Drivven will provide an evaluation netlist which contains a 5-minute time-bomb. 
• ModelSim test fixtures are available for simulation evaluation.

Documentation

J1850 VPW

J1850 PWM